A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs
作者： S. Ghosh
DOI: 10.1109/TCAD.1987.1270312
关键词:
摘要: A new approach to the timing verification of digital designs is introduced in this paper. The capable verifying synchronous and asynchronous including self-timed circuits [10]. Every component a circuit represented by description that may concurrently execute with other descriptions. Communication between scheduling descriptions are distributed every and, approach, parallelism be utilized relative ease. Conventional approaches such as SCALD [7], TV [5], one reported Hitchcock [4] limited only. has been verified through an implementation RDV system [3] at Stanford University. Descriptions models devices simplified AMD2903 architecture also presented
sci-hub.se 参考文章(7)
Charles L. Seitz, Self-Timed VLSI Systems California Institute of Technology. ,(1979)
Stephen A. Szygenda, Edward W. Thompson, Fault insertion techniques and models for digital logic simulation Proceedings of the December 5-7, 1972, fall joint computer conference, part II on - AFIPS '72 (Fall, part II). pp. 875- 884 ,(1972) , 10.1145/1480083.1480112
Marvin A. Wold, Design Verification and Performance Analysis design automation conference. pp. 264- 270 ,(1978) , 10.5555/800095.803101
Norman P. Jouppi, Timing Analysis for nMOS VLSI design automation conference. pp. 411- 418 ,(1983) , 10.5555/800032.800700
S. A. Szygenda, TEGAS2 - Anatomy of a general purpose test generation and simulation system for digital logic design automation conference. pp. 116- 127 ,(1972) , 10.1145/800153.804937
Robert B. Hitchcock, Timing Verification and the Timing Analysis Program design automation conference. pp. 446- 456 ,(1982) , 10.5555/800263.809264
Thomas M. McWilliams, Verification of timing constraints on large digital systems ,(1980)