Random address system for circuit modules

摘要: The wafer scale integrated circuit comprises an array of undiced chips or modules (10), each which includes a data storing processing circuit, e.g. dynamic RAM, and configuration logic. Channels (11) for control signals exist between module its (N, S, E W) neighbours target in the may be addressed by setting up path (12) through from entry to module. addressing is effected sending stream link commands, tells on neighbour. Each responds first command then sends stripped this command. In alternative embodiment commands are transmitted parallel, at least significant end strips it off shift direction before pass next A random forms unique set addressed, these sets being such that paths various form densely branching tree commencing