Memory interleave system
作者： Ishikawa c o Nec Computer Techno Ltd. Hisashi
DOI:
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摘要: A memory interleave system includes M (M is 2p 0 where p a natural number) banks, N (a CPUs, address generating units, and control units. Each bank plurality of memories. The CPUs output requests as access to the banks. request contains first which intra-bank in bank. units respectively correspond CPUs. unit receives from corresponding CPU, newly generates outputs second by using are contained request. performs on basis unit. selected
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