A low-cost susceptibility analysis methodology to selectively harden logic circuits

摘要: Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable complexity. In this paper we introduce low-cost analysis methodology that helps identifying most vulnerable circuit elements for hardening less computational effort orders of magnitude faster. Our experimental results show offers huge gain in terms (2,500× faster) comparison fault-injection based method produces within acceptable degree accuracy.