作者: Jerry A. Kreifels , Richard J. Durante , Mamun Rashid , Rodney R. Rozman
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摘要: An apparatus for testing a unit comprising an internal processor coupled to register by bus. The is programmed so that it can execute algorithm. When executed, the algorithm performs operation on unit. storing state datum. bus used access datum when executing comprises external disposed and interface switch processors receiving plurality of commands from processor. include command open trap command. If issued, causes between receives command, permits register.