Method and apparatus for controlling clocks in a processor with mirrored units
作者： Timothy G. McNamara , David Webber , Michael Billeci , Ching-Lung L. Tong
DOI:
关键词:
摘要: A method and apparatus for operating a clock in processor having asymmetrically mirrored base-mirror units is disclosed. The includes initializing base-unit mirror-unit of the to same state, starting mirror-unit-clock one cycle later than base-unit-clock.
lens.org 参考文章(6)
Hideo Oyamada, Minoru Shiga, Multi-processor system with fault detection ,(1993)
Mark A. Taylor, Paul A. Duffy, David J. Garcia, Real time comparison of integrated circuit operation ,(1994)
Ferenc Miklos Bozso, Yiu-Hing Chan, David Patrick Hillerud, Philip George Emma, Algirdas Joseph Gruodis, Scott Barnett Swaney, Recovery unit for mirrored processors ,(1996)
Charles L. Wallace, David G. Hanson, Mark A. Salser, Fault tolerant processor/memory architecture ,(1990)
Bradley D. Hoyt, Adrian L. Carbine, Donald D. Parker, Gary L. Brown, Rajesh Kumar, Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue ,(1994)
Charles Franklin Webb, Mark Steven Farrell, Mapping processor state into a millicode addressable processor state register array ,(1997)