作者: Hideo Oyamada , Minoru Shiga
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摘要: A bus coupling type multi-processor system is disclosed having multiple processor modules and a fault detection system. module includes first processor, second monitor including timer for measuring elapsed time, register storing flag indicating the operation of its own detector detecting either in or another module. starting circuit starts one clock period later than processor. comparator compares output from with to detect fault. set by reset signal When not module, detects this judges that has occurred within predetermined