A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

作者: Jinho Ko , Jongmoon Kim , Sanghyun Cho , Kwyro Lee

DOI: 10.1109/JSSC.2005.847326

关键词:

摘要: This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for operation. The receiver is composed RF preamplifier, down-conversion mixers, variable-gain channel filter, 2-bit analog-to-digital converter, full phase-locked-loop synthesizer including on-chip voltage controlled oscillator. Fabricated in 0.18-/spl mu/m CMOS technology, exhibits maximum gain 95 dB noise figures 8.5 7.5 L1 L2, respectively. An filter provides IF image rejection 20 control range over 60 dB. consumes 19 mW from 1.8-V supply while occupying 2.6-mm/sup 2/ die area ESD I/O pads.

参考文章(23)
M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland, A fully-integrated GPS receiver front-end with 40 mW power consumption international solid-state circuits conference. ,vol. 1, pp. 396- 397 ,(2002) , 10.1109/ISSCC.2002.993099
G. Montagna, G. Gramegna, I. Bietti, M. Franciotta, A. Baschirotto, P. De Vita, R. Pelleriti, M. Paparo, R. Castello, A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio IEEE Journal of Solid-state Circuits. ,vol. 38, pp. 1163- 1171 ,(2003) , 10.1109/JSSC.2003.813298
M. Cloutier, T. Varelas, C. Cojocaru, F. Balteanu, A 4-dB NF GPS receiver front-end with AGC and 2-b A/D custom integrated circuits conference. pp. 205- 208 ,(1999) , 10.1109/CICC.1999.777274
Jongmoon Kim, Sanghyun Cho, Jinho Ko, L1/L2 dual-band CMOS GPS receiver european solid-state circuits conference. pp. 87- 90 ,(2004) , 10.1109/ESSCIR.2004.1356624
P. Andreani, B. Essink, S. Mattisson, A CMOS g m -C polyphase filter with high image band rejection european solid-state circuits conference. pp. 272- 275 ,(2000)
J. Crols, M. Steyaert, An analog integrated polyphase filter for a high performance low-IF receiver symposium on vlsi circuits. pp. 87- 88 ,(1995) , 10.1109/VLSIC.1995.520698
Won Namgoong, S. Reader, T.H. Meng, An all-digital low-power IF GPS synchronizer IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 856- 864 ,(2000) , 10.1109/4.845189
F. Behbahani, H. Firouzkouhi, R. Chokkalingam, S. Delshadpour, A. Kheirkhahi, M. Nariman, M. Conta, S. Bhatia, A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection IEEE Journal of Solid-state Circuits. ,vol. 37, pp. 1721- 1727 ,(2002) , 10.1109/JSSC.2002.804355
F. Piazza, Qiuting Huang, A 1.57-GHz RF front-end for triple conversion GPS receiver IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 202- 209 ,(1998) , 10.1109/4.658621
B. Nauta, A CMOS transconductance-C filter technique for very high frequencies IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 142- 153 ,(1992) , 10.1109/4.127337