Optimizing routability in large-scale mixed-size placement

摘要: One of the necessary requirements for placement process is that it should be capable generating routable solutions. This paper describes a simple but effective method leading to reduction routing congestion and final routed wirelength large-scale mixed-size designs. In order reduce improve routability, we propose blocking narrow regions on chip. We also dummy-cell insertion inside characterized by reduced fixed-macro density. Our placer consists three major components: (i) channel performing neighbor-based inflation; (ii) large with density; (iii) pre-placement inflation detecting tangled logic structures in netlist minimizing maximum pin evaluated quality our using newly released DAC 2012 routability-driven contest designs compared results top four teams participated contest. The experimental reveal improves routability effectively reduces congestion.