An Application of ADD-Based Timing Analysis to Combinational Low Power Re-Synthesis

摘要: AnApplicationofADD-BasedTimingAnalysistoCombinationalLowPoerRe-SynthesisR. Iris BaharHyunwo o ChoyGary D. HachtelEnrico MaciizFabio SomenziUniversity of ColoradoDept. Electrical and Computer EngineeringBoulder, CO80309AbstractPower dissipation in technology mapped circuits can breducdbyperforminggatee-sizing,thatis,slowingdowngateswithoutdecreasingthespdoflogicnetwork.Recently we have proposed a symbolic proe-dure which exploits the compactness ADD datastructuretoaccuratelycalculatethearrivaltimesateachnodeofacircuitforanyprimaryinputvector.In this paper extend our timing analysis tool to thesymbolic calculation requird times slacks, andwe use information identify gates circuitthat be re-sized.The nice feature approachis that it takes into account presence false pathsnatural ly,thatis,falsepathsinthenetworkdonothave hand led by ad-hoc techniques.As shown bytheexperimentalresults,circuitse-synthesizedwiththe techniquewe present are guaranteedto at least as fast original implementations,butsmal lerandsubstantial lylesspower-consuming.Our methods inproves power consumptionon averageby 28% one case much 49%.1Intro ductionAsthecomplexity sp eedof VLSI chipsarecon-tinuously increasing, p ower consumption is b ecomingcriticalwithresp ecttoheatdissipationandcurrentdensity.PowerdissipationinCMOSdevicescanb ereducedby means precise architectural choices [1] accu-rate selection mapping algorithms [2, 3].However, even after thesedesign decisions eenmade, there still ro om improve quality thecircuitwithresp ectto itsp owerconsumption.Gatere-sizing[4]isthemostcommon approachthatcanThis work supp orted part NSF/DARPA grant MIP-9115432 SRC contract 92-DJ-206.yHyunwo Cho with Motorola Inc., Austin, TX 78735.zEnrico Macii also Politecnico di Torino,Dip.diAutomatica e Informatica, Torino, ITALY 10129.b applied mapp ed circuit order todecrease its dissipation.Gate re-sizing consistsof replacing some devices inthegatelibraryhavingsmallerareaand,therefore,smaller capacitiveload.Giventhatthep owerdissi-pated gate directly prop ortional outputcapacitance, reducing load leads reduction ofthe dissipated well reduc-tion chip area.The problem smaller slower; therefore, orderto preservethe ehavior circuit, not allthe re-sized; only ones non-critical, i.e., do elong criticalpath network, sloed down.Clearly, theapplicability metho d reduce thep heavily dep ends on theaccuracyprovided bythetiming ol inde-tecting paths calculating true delayof eing re-synthesized for low-p ower.It known most ective whendetailedtiminginformationisavailabletoidentifynon-criticalgatesofthecircuit.In[5]wehavpro-p osed symb olic pro cedure based Algebraic Deci-sion Diagrams (ADDs) [6] accurately calculate thearrival time output each any primaryinput vector.In pap er capability ofrequired informationto determine how re-sized with-outchangingtheoriginalsp eedofcircuit.Theniceprop ertyofourADD-basedre-synthesisto olisthatithandlescircuitswithfalsepathsinthesameway treatscircuitswhich arefalse path free.Thisisveryimp ortantinthecasegoaloptimizingp designs duced automaticsynthesisprogramstargetingareaasprimary ob jec-tive.In fact, has een exp erimentally observed thatin many cases area optimization intro duces pathsinto were originally free.