An integrated CAD environment for low-power design
作者： P. Landman , R. Mehra , J.M. Rabaey
DOI: 10.1109/54.500202
关键词:
摘要: This CAD environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. An integrated set analysis optimization tools spans design hierarchy, allowing designer make systematic, top-down exploration refinement solutions in area-time-power space. In case study-a low-power implementation digital bandpass filter-the yield more than an order magnitude savings power.
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ieeecomputersociety.org 参考文章(27)
F. Somenzi, Enrico Macii, G. Hachtel, R. Bahar, H. Cho, An Application of ADD-Based Timing Analysis to Combinational Low Power Re-Synthesis IWLPD-94: ACM/IEEE 1994 International Workshop on Low Power Design. pp. 39- 44 ,(1994)
Paul Eric Landman, Low-power architectural design methodologies University of California at Berkeley. ,(1995)
R.W. Brodersen, A. Chandrakasan, S. Sheng, Technologies for personal communications symposium on vlsi circuits. pp. 5- 9 ,(1991) , 10.1109/VLSIC.1991.760053
Anatomy of a Silicon Compiler Kluwer Academic Publishers. ,(1992) , 10.1007/978-1-4615-3570-6
Jacob Shekel, Analysis of linear networks Massachusetts Institute of Technology. ,(1957)
Jan M. Rabaey, Lisa M. Guerra, Exploring the Architecture and Algorithmic Space for Signal Processing Applications international conference on vlsi and cad. ,vol. 3, pp. 315- 319 ,(1993)
E.K. Tsern, A.C. Hung, T.H.Y. Meng, Video compression for portable communication using pyramid vector quantization of subband coefficients ieee workshop on vlsi signal processing. pp. 444- 452 ,(1993) , 10.1109/VLSISP.1993.404461
Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low-Power CMOS Digital Design IEICE Transactions on Electronics. pp. 371- 382 ,(1992)
P. Ashar, V. Tiwari, S. Malik, Technology Mapping for Low Power design automation conference. pp. 74- 79 ,(1993) , 10.1109/DAC.1993.203922
J.S. Ward, P. Barton, J.B.G. Roberts, B.J. Stanier, Figures of merit for VLSI implementations of digital signal processing algorithms IEE Proceedings F Communications, Radar and Signal Processing. ,vol. 131, pp. 64- 70 ,(1984) , 10.1049/IP-F-1:19840012