作者: Wing K. Huie
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摘要: An integrated circuit including CMOS transistors and an EPROM device by a method selectively implanting threshold adjusting atoms of P-type in the channel regions N-type while exposing whole area P-channel transistor. Subsequently, sources drains N-channel are implanted using gates as self-aligning mask portion. The PN-junction capacitance thereby kept low not subject to degrading effects implant. is also affected source drain capacitances there reduced so that speed all three types enhanced. Only high-yield process steps included.