Method of making a fast IGFET

作者: Wing K. Huie

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摘要: An integrated circuit including CMOS transistors and an EPROM device by a method selectively implanting threshold adjusting atoms of P-type in the channel regions N-type while exposing whole area P-channel transistor. Subsequently, sources drains N-channel are implanted using gates as self-aligning mask portion. The PN-junction capacitance thereby kept low not subject to degrading effects implant. is also affected source drain capacitances there reduced so that speed all three types enhanced. Only high-yield process steps included.

参考文章(12)
Mark A. Halfacre, David S. Pan, Alexander H. Owens, Method of making a CMOS EPROM with independently selectable thresholds ,(1984)
Shotaro Umebachi, Gota Kano, Hiromitsu Takagi, Iwao Teramoto, Method of making FET utilizing shadow masking and diffusion from a doped oxide ,(1980)
Werner A. Metz, Hubert O. Hayworth, Twin well single mask CMOS process ,(1984)
Eliezer Kinsbron, William T. Lynch, Thomas E. Smith, Fabrication of FETs ,(1983)
Martin Revitz, Joseph F. Shepard, James R. Gardiner, William A. Pliskin, Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon ,(1980)
Joseph P. Sadowski, David D. Kirkland, Frank J. Sigmund, Jerrell M. Gedaly, Method for fabricating a semiconductor read only memory ,(1980)