Computer system with high speed data transfer capabilities

摘要: The present invention is a computer system which can perform master unit controlled memory accesses at first rate, DMA operations second rate and burst of both types higher third rate. operation set up by performing standard access cycle, thus setting the dynamic random row address, then series fast, column address-only to same page memory. fast mode must be exited whenever boundary crossed, with recommencing thereafter. Wait states inserted in all type operations. Thirty-two bit units downshift or step down 16 respond burstable responding units. Timing diagrams controller state machines are disclosed.