Transparently inserting wait states into memory accesses when microprocessor in performing in-circuit emulation
作者： Steven M. Farrer , Mark J. Balmer
DOI:
关键词:
摘要: The invention provides a register, which when set to specific value, ensures that memory accesses take at least specified number of clock cycles. specifically introduces delays into the bank control register is configured operate in fast-CAS (fast column address strobe) mode operation. are introduced transparent values otherwise controls operation bank. delay by permits an in-circuit-emulation (ICE) system sufficient time transfer trace data from microprocessor ICE-base.
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