Method and apparatus for performance optimization in power-managed computer systems
作者： Michael R. Flannery
DOI:
关键词: Clock skew 、 CPU multiplier 、 Clock gating 、 Simulation 、 Reduction (complexity) 、 Underclocking 、 Clock rate 、 Synchronous circuit 、 Computer science 、 Power (physics) 、 Real-time computing
摘要: The performance of a computer system which use reduction clock speed to conserve power is enhanced by dynamically adjusting the minimum number cycles required for memory access ("wait states"). When decreases its speed, wait states decreased account longer cycle time. Likewise, when increases this invention determines whether any increase in required, and if so, implements such an increase.
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