作者: Samuel Fuller
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摘要: A secondary cache memory system is disclosed for use in a portable computer that increases performance while also conserving battery life. The includes controller controlling the transfer to and from memory, comprised of fast SRAM circuits. control status register with at least three bits power cache, insure data stored coherent memory. management logic checks contents register, monitors activity level processor. When processor determined be inactive, turns off by changing state bit register. Before doing so, however, second determine if some or all need flushed During up, another invalid, clears cache.