N+0.5 wait state programmable DRAM controller
作者： Jeffery M. Michelsen , Mitchell A. Stones
DOI:
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摘要: CPU system performance is improved by reducing the time required to complete a DRAM access microprocessors such as 386DX, 386SX and 80286 incorporating programmable controller therewith which permits consecutive accesses average N+0.5 processor wait states. The half state obtained forcing measure states in clock units are twice period of an independent which, turn, triggers RAS CAS assert de-assert. or thus able 1/2 earlier one memory cycle relative last. Early also provides for early de-assert so that data can be transferred to/from more quickly than previously possible.
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