Rapid Prototyping of Quaternion Multiplier: From Matrix Notation to FPGA-Based Circuits

摘要: In recent years, hypercomplex numbers called quaternions attract attention of many researchers the fields digital signal processing (DSP), control, computer graphics, telecommunications, and others. By using arithmetic, known algorithms can be improved or extended to 4 dimensions so as find new applications (Alexiadis & Sergiadis, 2009; Chan et al., 2008; Denis 2007; Ell Sangwine, Karney, Marion 2010; Parfieniuk Petrovsky, 2010a; Seberry Took M Tsui Zhou 2007). Current research is mainly focused on theoretical development quaternion-based algorithms, but one expect that, in course time, engineers scientists will implement them hardware, thus need building blocks, design insights, methodologies, tools. that use key operation quaternion multiplication, whose efficiency accuracy obviously determines same properties whole computational scheme a filter transform. Even though has been thoroughly investigated from mathematical point view (Howell Lafon, 1975), rather little about practical aspects implementing it hardware dedicated circuit. To best our knowledge, only two groups reported fixed-point multipliers. (Delosme Hsiao, 1990; Hsiao Delosme, 1996; 2000; 2010b; Petrovsky 2001; Verenik 2007), they considered various approaches computing constant-coefficient multiplication binary shifts additions: CORDIC, lifting, Distributed Arithmetic (DA), there no review developed schemes, which would allow compared inspire further research. The present chapter aims. first briefly facts achievements related multipliers and, by presenting novel CORDIC-Inside-Lifting architecture, show much do this field. second aim methodology results rapid prototyping different multiplier schemes Xilinx Virtex FPGA device. contents should useful persons interested computations, readers Rapid Prototyping Quaternion Multiplier: From Matrix Notation FPGA-Based Circuits 11