Sparse-Iteration 4D CORDIC Algorithms for Multiplying Quaternions

摘要: Novel 4D CORDIC algorithms and hardware architecture for multiplying quaternions are presented, aimed at constant-coefficient multipliers. In our solution, microrotations multiplications by hypercomplex numbers with only one non-zero imaginary part. Such transformations can be described using sparse matrices implemented less resources than the iteration of known quaternion algorithm. Chip area saved because computed a permutation network two-operand adders, without four-operand additions, which necessary in solution. The obtainable savings depend on implementation technology architectures adders bit shifters but as large 45 25 percent ASIC FPGA circuits, respectively. circuitry simplifications come cost slowing down computations: approach improves area-delay product, a single executed up to 15 faster conventional one, more usually achieve required accuracy. On other hand, identified two 2D CORDICs work parallel. This makes convergence analysis easier previous it is sufficient consider dimensions.