Reduce-by-feedback: timing resistant and DPA-aware modular multiplication plus: how to break RSA by DPA
DOI: 10.1007/978-3-642-33027-8_27
关键词:
摘要: We (re-) introduce the Reduce-By-Feedback scheme given by Vielhaber (1987), Benaloh and Dai (1995), Jeong Burleson (1997). We show, how to break RSA, when implemented with standard version of Reduce-by-Feedback or Montgomery multiplication, Differential Power Analysis. then modify avoid this attack. The modification is not possible for multiplication. We show that both original modified algorithm resist timing attacks. Furthermore, some VLSI-specific implementation details (delayed carry adder, re-use MUX tree logic) are provided.
springer.com
sci-hub.st 参考文章(23)
Wei Dai, Josh Benaloh, Computer-implemented method and computer for performing modular reduction ,(1995)
Ernest F. Brickell, A Fast Modular Multiplication Algorithm with Application to Two Key Cryptography international cryptology conference. pp. 51- 60 ,(1983) , 10.1007/978-1-4757-0602-4_5
Aggelos Kiayias, Moti Yung, Efficient Secure Group Signatures with Dynamic Joins and Keeping Anonymity Against Group Managers Progress in Cryptology – Mycrypt 2005. pp. 151- 170 ,(2005) , 10.1007/11554868_11
Sung-Ming Yen, Wei-Chih Lien, SangJae Moon, JaeCheol Ha, Power Analysis by Exploiting Chosen Message and Internal Collisions – Vulnerability of Checking Mechanism for RSA-Decryption Progress in Cryptology – Mycrypt 2005. pp. 183- 195 ,(2005) , 10.1007/11554868_13
Paul C. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems international cryptology conference. ,vol. 1109, pp. 104- 113 ,(1996) , 10.1007/3-540-68697-5_9
Marc Joye, Highly Regular Right-to-Left Algorithms for Scalar Multiplication cryptographic hardware and embedded systems. pp. 135- 147 ,(2007) , 10.1007/978-3-540-74735-2_10
Peter L. Montgomery, Modular multiplication without trial division Mathematics of Computation. ,vol. 44, pp. 519- 521 ,(1985) , 10.1090/S0025-5718-1985-0777282-X
Adam J. Elbirt, Christof Paar, Toward an FPGA architecture optimized for public-key algorithms Proceedings of SPIE. ,vol. 3844, pp. 33- 42 ,(1999) , 10.1117/12.359540
H. Sedlak, U. Golze, An RSA cryptography processor Microprocessing and Microprogramming. ,vol. 18, pp. 583- 590 ,(1986) , 10.1016/0165-6074(86)90094-3
Yong-Jin Jeong, W.P. Burleson, VLSI array algorithms and architectures for RSA modular multiplication IEEE Transactions on Very Large Scale Integration Systems. ,vol. 5, pp. 211- 217 ,(1997) , 10.1109/92.585224