VLSI array algorithms and architectures for RSA modular multiplication

摘要: We present two novel iterative algorithms and their array structures for integer modular multiplication. The are designed Rivest-Shamir-Adelman (RSA) cryptography based on the familiar Horner's rule, but use precalculated complements of modulus. problem deciding which multiples modulus to subtract in intermediate iteration stages has been simplified using simple look-up complement numbers, thus allowing a finer-grain pipeline. Both carry save adder scheme with module reduction performed each partial product results an output carry-save format. Regularity local connections make both suitable high-performance implementation FPGA's or deep submicron VLSI. processing nodes consist just one full adders multiplexor. stored numbers need be only when is changed, not affecting performance main computation. In cases, there exists bit-level systolic schedule, means can fully pipelined high also easily mapped linear arrays various space/time tradeoffs.