摘要: Systolic hardware realizations for two-dimensional finite-impulse-response (FIR) and infinite-impulse-response (IIR) digital filters are presented. The structure permits the 2-D input data to be scanned row-wise broadcasted one value at a time various processing elements. Shift registers used store required needed by recursive equation. A element can implemented in VLSI, as many of these satisfy order filter build total structure. >
sci-hub.se 参考文章(8)
M. Hatamian, G.L. Cash, A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS IEEE Journal of Solid-state Circuits. ,vol. 21, pp. 505- 513 ,(1986) , 10.1109/JSSC.1986.1052564
A. Venetsanopoulos, C. Nikias, Realization of two-dimensional digital filters by LU decomposition of their transfer function international conference on acoustics, speech, and signal processing. ,vol. 9, pp. 160- 163 ,(1984) , 10.1109/ICASSP.1984.1172470
G. Lampropoulos, M. Fahmy, A new realization fo 2-D digital filters IEEE Transactions on Acoustics, Speech, and Signal Processing. ,vol. 35, pp. 533- 542 ,(1987) , 10.1109/TASSP.1987.1165173
S. Erfani, B. Peikari, Digital design of two-dimensional LC structures IEEE Transactions on Circuits and Systems. ,vol. 28, pp. 75- 77 ,(1981) , 10.1109/TCS.1981.1084898
Kung, Why systolic architectures IEEE Computer. ,vol. 15, pp. 300- 309 ,(1982) , 10.1109/MC.1982.1653825
S. Mitra, A. Sagar, N. Pendergrass, Realizations of two-dimensional recursive digital filters IEEE Transactions on Circuits and Systems. ,vol. 22, pp. 177- 184 ,(1975) , 10.1109/TCS.1975.1084018
S. Chakrabarti, S. Mitra, Decision methods and realization of 2-D digital filters using minimum number of delay elements IEEE Transactions on Circuits and Systems. ,vol. 27, pp. 657- 666 ,(1980) , 10.1109/TCS.1980.1084877
G. A. Lampropoulos, M. M. Fahmy, A New Realization for 2-D Digital Filters ,(1987)