作者: Sebastian T. Ventrone , Emory D. Keller , Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza
DOI:
关键词:
摘要: A system and method are described for separating the bulk connections FETs on a semiconductor wafer from supply rails, testing to determine if shift in threshold voltage, V T , of certain devices within wafer, as defined by bulk-wells, can remove an AC defect IC circuit, tailoring voltage or voltages applied nodes, post-manufacture, such that integrated circuit meets its performance targets is sorted more valuable level. The requires generating gate level netlist IC's circuitry performing timing calculations these netlists using static analyses, functional delay simulations, activity testing. failures then correlated respective circuits, worst case slack circuits investigated, proposed changes employed hardware.