Vertical transistor with horizontal gate layers

作者： Leonard Forbes

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摘要: Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in high density flash electrically erasable and programmable read only (EEPROM) or logic field (FPLA). The transistor is field-effect (FET) having an isolated (floating) that controls electrical conduction between source regions drain regions. If particular floating charged stored electrons, then the will not turn on provide indication of data at this location within EEPROM act as absence FPLA. includes densely packed cells, each cell semiconductor pillar providing shared for two vertical have control gates overlaying distributed opposing sides pillar. Both bulk silicon-on-insulator embodiments provided. store single bit represent function, area 2F 2 needed per respective logic, where F minimum lithographic feature size.

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