AC-Plus Scan Methodology for Small Delay Testing and Characterization

摘要: Small delay defects escaping traditional testing could cause a device to malfunction in the field and thus detecting these is often necessary. To address this issue, we propose three test modes new methodology called AC-plus scan, which versatile clocks can be generated on chip by embedding an all-digital phase-locked loop (ADPLL) into circuit under (CUT). scan executed in-house wireless platform HOY system. The first mode of our provides more efficient way measure longest path associated with each pattern. Experimental result shows that method greatly reduce time 81.8%. second designed for volume production test. It effectively detect small provide fast characterization those defective chips further processing. This used help predict are likely fall victim operational failure field. third extract waveform flip-flop's output real chip. made possible taking advantage almost unlimited memory provides, so easily store great data reconstruct post-silicon debugging. We have successfully fabricated Viterbi decoder such inside demonstrate its capability.