Measurement of digital circuit simulation test coverage utilizing BDDs and state bins
作者： Richard Raimi , Carl Pixley
DOI:
关键词:
摘要: Measurement of the test coverage digital simulation electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target (64) and an Environment (62). The (62) models behavior inputs to (64). translated into implicit FSM representations utilizing BDDs. State Bin Transition Relation formed which represents allowable transitions among user-specified sets states or Bins, representation reachable Bins built (94). comparison made (102) between data accumulated over one more simulations (40) contained in Bins. Output (52) then generated showing circuit were weren't visited allowed by taken during simulations.
google.nl 参考文章(19)
Ronald A. Kita, Sylvia C. Tremblay, Thomas M. Lynch, Method and apparatus for generating tests for structures expressed as extended finite state machines ,(1993)
Carl Pixley, Apparatus and method for determining sequential hardware equivalence ,(1991)
Chih-Chung Chen, Patrick Yin, Owen S. Bair, Automatic logic model generation from schematic data base ,(1992)
S. Malik, A.R. Wang, R.K. Brayton, A. Sangiovanni-Vincentelli, Logic verification using binary decision diagrams in a logic synthesis environment international conference on computer aided design. pp. 6- 9 ,(1988) , 10.1109/ICCAD.1988.122451
Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley, Synchronizing sequences and symbolic traversal techniques in test generation Journal of Electronic Testing. ,vol. 4, pp. 19- 31 ,(1993) , 10.1007/BF00971937
Randal E. Bryant, Symbolic Boolean manipulation with ordered binary-decision diagrams ACM Computing Surveys. ,vol. 24, pp. 293- 318 ,(1992) , 10.1145/136035.136043
Satoshi Kowatari, Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose, Automatic test program generation for pipelined processors international conference on computer aided design. pp. 580- 583 ,(1994) , 10.5555/191326.191566
Bryant, Graph-Based Algorithms for Boolean Function Manipulation IEEE Transactions on Computers. ,vol. 35, pp. 677- 691 ,(1986) , 10.1109/TC.1986.1676819
J.R. Burch, E.M. Clarke, D.E. Long, K.L. McMillan, D.L. Dill, Symbolic model checking for sequential circuit verification IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 13, pp. 401- 424 ,(1994) , 10.1109/43.275352