Process identifier-based cache information transfer
作者： Steven R. Carlough , Fadi Y. Busaba , Brian R. Prasky , Christopher A. Krygowski , Chung-Lung K. Shum
DOI:
关键词:
摘要: Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect includes sending, by a first core processor, PID associated with miss in local second processor. Another determining that is listed table cache. Yet another on being cache, plurality entries directory are PID. pushing each determined from
google.de 参考文章(11)
Robert W. Wisniewski, Robert B. Tremaine, Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller ,(2009)
Shuji Yamamura, Kuniki Morita, Arithmetic processing device and controlling method thereof ,(2012)
Yaoqing Gao, Tong Chen, Managing multiple speculative assist threads at differing cache levels ,(2009)
Srihari Makineni, Ravishankar Iyer, Jaume Abella, Donald Newell, Jaideep Moses, Antonio Gonzalez, Josep M. Codina, Enric Gibert, Pedro Lopez, Fernando Latorre, Jose-Alejandro Pineiro, Ramesh G. Illikkal, Cache sharing based thread control ,(2007)
Erik G. Hallnor, Rameshkumar G. Illikkal, Ravishankar Iyer, Donald K. Newell, Martin G. Dixon, Li Zhao, Monitoring cache usage in a distributed shared cache ,(2009)
Kenta Yasufuku, Yasuhiko Kurosawa, Hiroo Hayashi, Mitsuo Saito, Shigeaki Iwasa, Seiji Maeda, Virtual address cache memory, processor and multiprocessor ,(2010)
Thomas R. Puzak, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Selective cache-to-cache lateral castouts ,(2009)
R. Iyer, On modeling and analyzing cache hierarchies using CASPER 11th IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer Telecommunications Systems, 2003. MASCOTS 2003.. pp. 182- 187 ,(2003) , 10.1109/MASCOT.2003.1240655
Raymond Tetrick, Ram Huggahalli, Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system ,(2003)