Phase locked loop having integration gain reduction

摘要: A non-linear integrated phase locked loop circuit includes a detector for receiving data signal and clock pulse outputting pump-up pump-down signal, divider connected to the producing first output at predetermined multiples of second signal. pulsed filter or integrator is providing frequency control voltage controlled oscillator. three state amplifier The oscillator corresponding output. In embodiment, outputs polarity an enable along with incrementor/decrementor increment decrement