Gigabit logic operation with enhancement-mode GaAs MESFET IC's
作者： T. Mizutani , N. Kato , K. Osafune , M. Ohmori
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摘要: Enhancement-mode GaAs MESFET IC's have been fabricated using electron-beam lithography. A recessed-gate structure to reduce the gate-to-source resistance and an air-bridge overlay interconnect stray capacitance were employed. 30-ps delay time with associated power dissipation of 1.9 mW is obtained a 0.6 × 20-µm gate MESFET, which highest speed among FET logics. Divide-by-eight counter has exhibited 3.8-GHz maximum clock frequency 1.2 mW/gate.
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