Logic circuit verification device for semiconductor integrated circuit
作者： Toshinori Inoshita , Yoshio Inoue , Hiroyuki Mori , Yasuo Moriguchi
DOI:
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摘要: A logic verification apparatus for a semiconductor integrated circuit classifies program described in HDL into connection information of synchronous portion and asynchronous portion, converts the increases portions function which can be verified by cycle based simulation/static timing unit, thus making it possible to shorten time verification.
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