Semiconductor device having a multilayered wiring structure

作者: Masanori Kinugasa , Munenobu Kida , Shuichi Shoji , Kohichi Takayama

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摘要: At least one slit having a predetermined shape is formed around contact region of lower wiring layer on substrate, and an insulating portion integrally with embedded in this slit. This the has hole located at position corresponding to region. Since as rectangular projecting projects into downwardly from rigid layer, positional errors caused by thermal expansion annealing upper can be suppressed, abnormal geometry such projection prevented. In addition, semiconductor device free interwiring short-circuiting excellent flatness obtained.

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