作者: Alexander Czutro , Ilia Polian , Piet Engelke , Sudhakar M. Reddy , Bernd Becker
DOI: 10.1109/ATS.2009.31
关键词:
摘要: SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large sets. We present a dynamic compaction procedure for ATPG which utilizes internal data structures of the SAT solver extract essential fault detection conditions and generate patterns cover multiple faults. complement this technique by state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained an industrial benchmark circuit suite show that new method outperforms earlier static approaches approximately 23%.