Dynamic Compaction in SAT-Based ATPG

作者: Alexander Czutro , Ilia Polian , Piet Engelke , Sudhakar M. Reddy , Bernd Becker

DOI: 10.1109/ATS.2009.31

关键词:

摘要: SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large sets. We present a dynamic compaction procedure for ATPG which utilizes internal data structures of the SAT solver extract essential fault detection conditions and generate patterns cover multiple faults. complement this technique by state-of-the-art forward-looking reverse-order simulation procedure. Experimental results obtained an industrial benchmark circuit suite show that new method outperforms earlier static approaches approximately 23%.

参考文章(14)
Niklas Eén, Niklas Sörensson, An Extensible SAT-solver theory and applications of satisfiability testing. ,vol. 2919, pp. 502- 518 ,(2003) , 10.1007/978-3-540-24605-3_37
Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, Digital Systems Testing and Testable Design ,(1990)
P. Engelke, S.M. Reddy, B. Becker, A. Czutro, I. Polian, M. Lewis, TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis international conference on vlsi design. pp. 227- 232 ,(2009) , 10.1109/VLSI.DESIGN.2009.20
Matthew Lewis, Tobias Schubert, Bernd Becker, Multithreaded SAT Solving asia and south pacific design automation conference. pp. 926- 931 ,(2007) , 10.1109/ASPDAC.2007.358108
I. Pomeranz, L.N. Reddy, S.M. Reddy, COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS international test conference. pp. 194- 203 ,(1991) , 10.1109/TEST.1991.519510
J. Paul Roth, Diagnosis of automata failures: a calculus and a method Ibm Journal of Research and Development. ,vol. 10, pp. 278- 291 ,(1966) , 10.1147/RD.104.0278
P. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli, Combinational test generation using satisfiability IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 15, pp. 1167- 1176 ,(1996) , 10.1109/43.536723
T. Larrabee, Efficient generation of test patterns using Boolean difference Proceedings. 'Meeting the Tests of Time'., International Test Conference. pp. 795- 801 ,(1989) , 10.1109/TEST.1989.82368
I. Pomeranz, S.M. Reddy, Forward-looking fault simulation for improved static compaction IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 20, pp. 1262- 1265 ,(2001) , 10.1109/43.952743