Analogue to digital converter
作者： John B. Hughes , William Redman-White , Mark Bracey
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摘要: (57) Abstract A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each stage an input (40) for receiving sampled and held which is via switch (S41) first memory (M42) (S40) second (M41). The output the (M41) fed (S44) one summing junction (48). (S42) comparator (C43) whose clocked into latch (L44) Q (45) as result conversion. also (46) (48) (S43) form residue signal application (47) next in pipeline. advantage that from using only thus reducing transmission loss corruption by 'kick back' avoided further parallel with path
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