Future trends in microprocessors: out-of-order execution, speculative branching and their CISC performance potential
作者： A. Peleg , U. Weister
关键词:
摘要: Current microprocessors with one execution core are already reaching the performance limit of close to Instruction Per Cycle. Thus, in order comply existing market demands a /sup approximately /1.5X improvement each year, new ideas and techniques needed for designing future Running instructions out order, parallel on multiple units, coupled resolving dependencies between (data or control flow), can provide expected, utilizing more fine grain parallelism. This paper surveys some these techniques, presents conceptual CISC Superscalar microprocessor model incorporating them. Its potential is evaluated via trace driven software simulator. >
sci-hub.se 参考文章(17)
Lee, Smith, Branch Prediction Strategies and Branch Target Buffer Design IEEE Computer. ,vol. 17, pp. 6- 22 ,(1984) , 10.1109/MC.1984.1658927
S. McFarling, J. Hennesey, Reducing the cost of branches international symposium on computer architecture. ,vol. 14, pp. 396- 403 ,(1986) , 10.1145/17356.17402
Robert M. Keller, Look-Ahead Processors ACM Computing Surveys. ,vol. 7, pp. 177- 195 ,(1975) , 10.1145/356654.356657
J.E. Smith, Dynamic instruction scheduling and the Astronautics ZS-1 IEEE Computer. ,vol. 22, pp. 21- 35 ,(1989) , 10.1109/2.30730
D. W. Anderson, F. J. Sparacio, R. M. Tomasulo, The IBM System/360 model 91: machine philosophy and instruction-handling Ibm Journal of Research and Development. ,vol. 11, pp. 8- 24 ,(1967) , 10.1147/RD.111.0008
P. Y T Hsu, E. S. Davidson, Highly concurrent scalar processing international symposium on computer architecture. ,vol. 14, pp. 386- 395 ,(1986) , 10.1145/17356.17401
James E. Thornton, Design of a Computer: The Control Data 6600 ,(1970)
Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman, A VLIW architecture for a trace scheduling compiler ACM SIGOPS Operating Systems Review. ,vol. 21, pp. 180- 192 ,(1987) , 10.1145/36204.36201
N. P. Jouppi, D. W. Wall, Available instruction-level parallelism for superscalar and superpipelined machines architectural support for programming languages and operating systems. ,vol. 17, pp. 272- 282 ,(1989) , 10.1145/68182.68207
A. R. Pleszkun, G. S. Sohi, The performance potential of multiple functional unit processors ACM SIGARCH Computer Architecture News. ,vol. 16, pp. 37- 44 ,(1988) , 10.1145/633625.52405