Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing

摘要: With the rapidly increasing test time of semiconductor testing, trend is currently toward improving parallelism by exploiting multi-site testing. However, excessive I/O channels and power consumption lead to degradation testing efficiency owing limited number tester I/Os capacity. In this paper, we present an advanced low pin count architecture for efficient in semiconductors. To achieve this, scan chain routing method first exploited reduce during scan-based through a cluster-based approach, which compatible with compression architecture. Subsequently, new proposed encode patterns enable each device-under-test (DUT) input using unique properties tri-state detector boundary The experimental results show decrease requirements consumption. Based on these improvements, application (TAT) was significantly reduced ISCAS’89 IWLS’05 OpenCores benchmark circuits compared previous methods, without heavy burden additional H/W area overhead.