A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability

摘要: Wafer testing (wafer sort) is used in the semiconductor industry to reduce test costs. High parallelism important application time. However, increasing becoming more difficult because elements that drive costs are increases pin count of system on chip (SOC), and required automated equipment (ATE) channels. While need for has been growing, a reliability problem which fault distribution causes good devices under (DUT) be improperly tested concern. To achieve high reliability, we propose novel, massively parallel method using multi-root. In addition, develop setup setting root-DUT location path all DUTs. Using proposed wafer method, data can transferred between ATE dies multi-roots. The experimental results ITC 02 SOC benchmarks show up 90%, nearly 94.84% without affecting yield.