Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

摘要: As the circuit complexity increases, number of internal nodes increases proportionally, and individual are less accessible due to limited available I/O pins. To address problem, we proposed power line communications (PLCs) at IC level, specifically dual use pins distribution networks for application/ observation test data as well delivery power. A PLC receiver presented in this paper intends demonstrate proof concept, transmission through lines. The main design objective is robust operation under variations droops supply voltage rather than high speed. designed fabricated CMOS 0.18- $\mu \text{m}$ technology a 1.8 V. measurement results show that can tolerate drop up 0.423 V rate 10 Mb/s. dissipation 3.26 mW supply, core area 74.9 {\rm m} \times 72.2~\mu .