Opportunities for Scaling FET's for Gigascale Integration (GSI)

摘要: Using two-and three dimensional analytical and numerical models, scaling limits derived from small-geometry degradation of subthreshold characteristics are compared for six different FET structures in bulk Si, SOI GaAs technologies. For Si devices, the low impurity channel MOSFET can be scaled down to L min = 0.045?m dual gate 0.028?m. The MESFET 0.13?m AlGaAs/GaAs MODFET 0.095?m. key physical effect which enables small values is relative strength coupling between charge distributions.