Memory controller with interacting state machines

摘要: A memory controller for controlling a multiple bank DRAM comprises pool/queue state machine, plurality of transaction processor machines, command arbitor and preferably one machine each in the DRAM. As transactions are received by controller, they allocated to machines. The receiving first checks if corresponding read/write address is available. Once available, then sends RAS CAS requests request arbitor. receives this arbitrates between it other pending (both from machines precharge machines). When activated particular detects that on output, becomes active, eventually issue