Method for reducing the number of coherency cycles within a directory-based cache coherency memory system utilizing a memory state cache

摘要: An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data memories, shared memory, and employing centralized/distributed directory-based coherency maintaining consistency between lines of memory within the memories. The includes steps of: establishing default SHARED represented said memory; reading previously stored entry prior to entry, being associated with at least one castout operation update assigning each containing is OWNED. Since most are replacement, setting state, rather than uncached reduces number invalidate which must be performed during replacements.