N-way set associative cache memory and control method thereof
作者： Tokuzo Kiyohara , Hazuki Okabayashi , Keisuke Kaneko , Takao Yamamoto , Ryuta Nakanishi
DOI:
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摘要: The cache memory in the present invention is an N-way set-associative including a control register which indicates one or more ways among N ways, unit activates way indicated by said register, and updating updates contents of register. restricts at least replacement, for other than active
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