Synchronous switching in high-speed digital-to-analog converter using quad synchronizing latch
作者： Bruno M.S. Santos , Carlos M.A. Azeredo-Leme , Antonio I.R. Leal
DOI:
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摘要: A synchronizing circuit compatible with a quad switching scheme in digital-to-analog converter (DAC) to synchronize turning on or off of switches for steering current differential output. The receives signals from decoder and synchronizes control the by clock signal. In one embodiment, includes predictor latch circuit. may include four sets cross-coupled inverters where set are activated at time. By using conjunction scheme, linearity analog output DAC can be improved data dependent noise removed reduced.
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