Delay line synchronizer apparatus and method
作者： Paul A. LaBerge
DOI:
关键词:
摘要: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve pseudo-synchronous phase relationship between clock signals of different domains when the time from which one is output changed.
google.ch 参考文章(266)
Danny Chin, Kazuo Katsuki, Donald J. Sauer, Bus structure for multiprocessor system having separated processor section and control/memory section ,(1994)
William E. Steels, Jose J. Picazo, Network hub with integrated bridge ,(1992)
Wendell P. Noble, Semiconductor structure having an optical signal path in a substrate and method for forming the same ,(1997)
Mark Horowitz, Michael Farmwald, Apparatus for synchronously generating clock signals in a data processing system ,(1992)
Karl H. Mauritz, Paul S. Levy, System having multiple agents on optical and electrical bus ,(2002)
Jeffrey Jay Rooney, Dynamic buffer allocation for a computer system ,(1997)
Jeffrey F. Harness, Memory controller with burst addressing circuit ,(1996)
Patrick Allen Harkin, Stuart Hecht, Ronald Anthony Shipp, Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering ,(1995)
Robert Woodruff, Oscar Pinto, Communicating data over a communication link ,(2003)
Gary J. Piccirillo, Kenneth T. Chin, Robert A. Lester, Phillip M. Jones, Jerome J. Johnson, C. Kevin Coffee, Michael J. Collins, Jeffrey C. Stevens, Computer system with adaptive memory arbitration scheme ,(2001)