Power switch ramp rate control using daisy-chained flops
作者： Shingo Suzuki , Conrad H. Ziesler , Daniel C. Murray , Vincent R. von Kaenel , Toshinari Takayanagi
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摘要: In an embodiment, integrated circuit may include one or more power managed blocks and a manager circuit. The be configured to generate block enable for each clock. local enables various switches in the block, staggering over two clock cycles. particular, set of series-connected flops that receive from output flop coupled respective enabled those switches. change current flow due enabling and/or disabling thus controlled. frequency defined value independent process, voltage, temperature conditions
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