A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS
作者： Bo Zhang , A. Nazemi , A. Garg , N. Kocaman , M. R. Ahmadi
DOI: 10.1109/ISSCC.2013.6487625
关键词:
摘要: Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy links, such as backplanes (KR) multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially MMF applications, due to complexity pulse response dynamic nature impairment. The reach backplane channels can also be extended, providing flexibility system design. Applications 10G SFP+ DAC have less loss; consequently, slicer-based binary is more viable low-power solution. This work describes AFE dual-path that uses both ADC path slicer multi-standard applications 40nm CMOS.
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