A Reference-Less Single-Loop Half-Rate Binary CDR
作者： Mohammad Sadegh Jalali , Ali Sheikholeslami , Masaya Kibune , Hirotaka Tamura
DOI: 10.1109/JSSC.2015.2429714
关键词:
摘要: This paper proposes a half-rate single-loop reference-less binary CDR that operates from 8.5 Gb/s to 12.1 (36% capture range). The high range is made possible by adding novel frequency detection mechanism which limits the magnitude of phase error between input data and VCO clock. proposed detector produces three phases data, feeds into minimizes error. detector, implemented within 10 in Fujitsu's 65 nm CMOS, consumes 11 mW improves up 6 $\times $ when it activated.
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