6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS

摘要: Baud-rate clock and data recovery circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received only once per UI [1,2]. This reduces number of front-end comparators distribution networks [1]. However, current baud-rate CDRs require an external reference [1,2], adding to system complexity pin count generation. While frequency detectors (FDs) allow CDR operate without a across wide capture range [3–5], FDs not designed for CDRs. As well, rely on sharp edges significant ISI caused channel loss at high rates [3–5]. work presents reference-less that operates from 22.5Gb/s 32Gb/s with up −14.8dB Nyquist. An FD scheme is proposed automatically controls adjustable PD correct any error. eliminates need separate acquisition loop CDR. The CDR, CTLE 1-tap DFE, fabricated 28nm CMOS. entire consumes 3.2pJ/b PRBS-31.