作者: J. Savoj , B. Razavi
关键词:
摘要: A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator half-rate phase/frequency detector with automatic retiming. Fabricated in 0.18-/spl mu/m CMOS technology an area of 1.75/spl times/1.55 mm/sup 2/, the exhibits capture range 1.43 GHz, rms jitter 0.8 ps, peak-to-peak 9.9 bit error rate 10/sup -9/ pseudorandom sequence 2/sup 23/-1. The power dissipation excluding output buffers is 91 mW from 1.8-V supply.