Scalable on chip network

作者: Ned D. Garinger , Mark W. Naumann , Martin L. Dorr , Gary A. Walker

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摘要: A scalable OCN for supporting an application using processing elements integrated in IC including ports, interconnect, port interfaces, and arbiter. Each conforms to a consistent interface protocol regardless of number frequency operation, maximum datum width or data path concurrency. The interconnect has concurrency, includes selectable paths between any two ports enable transfer datums the ports. formulates packets transmission receives via corresponding where each packet comprising one more datums. arbiter controls source destination Pipeline stages may be added support selected clock frequency. component library bus gasket, components.

参考文章(16)
Peter Dau Geiger, Joel Roger Davidson, Sanjay Raghunath Deshpande, Praveen S. Reddy, Lawrence Joseph Powell, II Manuel Joseph Alvarez, Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system ,(1999)
Barton J. Sano, James B. Keller, Manu Gulati, Koray Oner, Laurent R. Moll, Joseph B. Rowlands, System having interfaces and switch that separates coherent and packet traffic ,(2002)
Gopalakrishnan Janakiraman, Rajendra Kumar, Tsen-Gong Jim Hsu, Padmanabha I. Venkitakrishnan, Scalable system control unit for distributed shared memory multi-processor systems ,(1999)
Randal S. Passint, Greg Thorson, Michael B. Galles, Hybrid hypercube/torus architecture ,(1997)
Pierre Guerrier, Alain Greiner, A generic architecture for on-chip packet-switched interconnections design, automation, and test in europe. pp. 250- 256 ,(2000) , 10.1145/343647.343776
Byong M. Shin, Harry Miller, Kwong Dong Chil, Expandable shoe and shoe assemblies ,(2004)