Clocked comparator with offset reduction
作者： De Plassche Rudy Johan Van
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摘要: In a clocked comparator with offset reduction differential amplifier (5) amplifies the voltage difference between input terminals (1, 2) and (Voff) in first state of clock signal stores said as charge capacitors (C1, C2), which second are coupled to inputs (3, 4) such way that owing positive feedback behaves flip-flop whose decision threshold is independent voltage.
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